US 12,148,388 B2
Light-emitting control shift register and method for controlling the same, gate driving circuit, display apparatus and method for controlling the same
Zhidong Yuan, Beijing (CN); Yongqian Li, Beijing (CN); Pan Xu, Beijing (CN); and Can Yuan, Beijing (CN)
Assigned to HEFEI BOE JOINT TECHNOLOGY CO., LTD., Anhui (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/921,677
Filed by Hefei BOE Joint Technology Co., Ltd., Anhui (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Nov. 8, 2021, PCT No. PCT/CN2021/129312
§ 371(c)(1), (2) Date Oct. 27, 2022,
PCT Pub. No. WO2022/237095, PCT Pub. Date Nov. 17, 2022.
Claims priority of application No. 202110513516.6 (CN), filed on May 11, 2021.
Prior Publication US 2024/0233650 A1, Jul. 11, 2024
Int. Cl. G09G 3/3266 (2016.01); G09G 3/20 (2006.01); G09G 3/3233 (2016.01); G11C 19/28 (2006.01)
CPC G09G 3/3266 (2013.01) [G09G 3/2096 (2013.01); G09G 3/3233 (2013.01); G11C 19/28 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2340/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A light-emitting control shift register, comprising:
an input circuit electrically connected to a first signal input terminal and a first clock signal terminal; wherein the input circuit is configured to output a signal of the first signal input terminal under a control of a signal from the first clock signal terminal;
a pulse width adjustment circuit electrically connected to the input circuit, an enable signal terminal, a second signal input terminal, a second clock signal terminal and a pull-up node; wherein the pulse width adjustment circuit is configured to transmit the signal output from the input circuit to the pull-up node under a control of a signal from the enable signal terminal; and the pulse width adjustment circuit is further configured to output a signal of the second clock signal terminal to the pull-up node under a control of a signal from the second signal input terminal;
a pull-up circuit electrically connected to the pull-up node, a first voltage terminal and a signal output terminal; wherein the pull-up circuit is configured to output a voltage of the first voltage terminal to the signal output terminal under a control of the pull-up node;
a pull-down control circuit electrically connected to the first clock signal terminal, the first voltage terminal, the pull-up node and a second voltage terminal; wherein the pull-down control circuit is configured to output the voltage of the first voltage terminal under a control of signals from the pull-up node, the first clock signal terminal and the first voltage terminal; and the pull-down control circuit is further configured to output a voltage of the second voltage terminal under the control of the pull-up node; and
a pull-down circuit electrically connected to the pull-down control circuit, the signal output terminal and the second voltage terminal; wherein the pull-down circuit is configured to pull down a voltage of the signal output terminal to the voltage of the second voltage terminal under a control of the voltage from the first voltage terminal.