| CPC G09G 3/3233 (2013.01) [G09G 3/035 (2020.08); G09G 3/32 (2013.01); G09G 2300/0426 (2013.01); H10K 59/1213 (2023.02)] | 16 Claims |
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1. A display device, comprising:
a stretchable lower substrate;
a pattern layer disposed on the stretchable lower substrate and including:
a plurality of plate patterns; and
a plurality of line patterns, each of the plurality of line patterns extending from one of the plurality of plate patterns to another of the plurality of plate patterns;
a plurality of pixels each respectively disposed on each of the plurality of plate patterns, at least one pixel on each plate pattern, each of the plurality of pixels including:
a driving transistor on the plate pattern, the driving transistor including a gate electrode;
a storage capacitor on the plate pattern, the storage capacitor including an intermediate metal layer that overlaps the gate electrode, the intermediate metal layer acting as a first electrode of the storage capacitor and the gate electrode of the driving transistor acting as a second electrode of the storage capacitor;
an interlayer insulating layer positioned between the intermediate metal layer and the gate electrode of the driving transistor, the interlayer insulating layer acting as a dielectric for the storage capacitor;
a planarization layer, the planarization layer extending from one of the plurality of line patterns to another of the plurality of line patterns; and
a plurality of connection lines disposed on each of the plurality of line patterns to connect the plurality of pixels, the plurality of connection lines being in contact with an upper surface of the planarization layer, a sidewall of the planarization layer and an upper surface of the pattern layer,
wherein each pixel of the plurality of pixels includes at least one light emitting element, the driving transistor, the storage capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor, each of which are positioned on a respective single plate pattern of the plurality of plate patterns,
wherein a constant power voltage is applied to the storage capacitor,
wherein the first electrode of the storage capacitor is directly connected to an initialization voltage line, and the second electrode of the storage capacitor is connected to the gate electrode of the driving transistor.
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