| CPC G09G 3/3225 (2013.01) [G09G 2300/0426 (2013.01)] | 18 Claims |

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1. A display panel, comprising:
a plurality of light emitting units; and
a plurality of pixel driving circuits for driving the plurality of light emitting units to emit light, comprising:
a first pixel driving circuit layer comprising at least one transistor;
a capacitor electrically connected to the at least one transistor of the first pixel driving circuit layer, and comprising a first electrode plate electrically connected to a first voltage line;
a second pixel driving circuit layer arranged on the capacitor, wherein the second pixel driving circuit layer comprises at least one transistor;
wherein an orthogonal projection of said at least one transistor of the second pixel driving circuit layer on the first electrode plate at least partially overlaps with the first electrode plate;
gates of transistors of the second pixel driving circuit layer are arranged on the first electrode plate, and at least some of the gates of the transistors of the second pixel driving circuit layer are electrically connected to a signal line; and
the first electrode plate comprises vias through which some of the transistors of the second pixel driving circuit layer are electrically connected with corresponding transistors of the first pixel driving circuit layer;
wherein the first pixel driving circuit layer comprises a first transistor, and the display panel comprises a first semiconductor layer, a first metal layer, a second metal layer, and a second semiconductor layer arranged in different layers;
wherein the first semiconductor layer comprises a first active portion of the at least one transistor of the first pixel driving circuit layer;
the second semiconductor layer comprises a second active portion of the at least one transistor of the second pixel driving circuit layer;
the first metal layer comprises a gate of the first transistor, and the gate of the first transistor doubles as a second electrode plate of the capacitor; and
the second metal layer comprises the first electrode plate, wherein an orthogonal projection of the gate on a horizontal plane at least partially overlaps with an orthogonal projection of the first electrode plate on the horizontal plane; and
wherein the orthogonal projection of the gate on the horizontal plane overlaps with an orthogonal projection of the second active portion on the horizontal plane, and/or the orthogonal projection of the first electrode plate on the horizontal plane partially overlaps with the orthogonal projection of the second active portion on the horizontal plane.
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