| CPC G09G 3/32 (2013.01) [G09G 2300/026 (2013.01); G09G 2310/08 (2013.01)] | 20 Claims |
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1. A tiling display apparatus, comprising:
a plurality of display modules connected to one another to configure a screen;
a set board configured to output an input data enable signal and image data synchronized therewith to one of the plurality of display modules;
first to Nth timing controllers configured for the plurality of display modules, the first to Nth timing controllers are sequentially connected to one another in a first direction through a first interface line based on a cascading scheme and configured to receive the input data enable signal and the image data at different timings which are sequentially delayed and synchronize a display time of the image data on the basis of an independently generated output data enable signal, where N is a natural number of 3 or more, and
a display panel configured to have a plurality of pixels for displaying an input image corresponding to the image data,
wherein, by using a current-stage input data enable signal received from an adjacent front-stage timing controller through the first interface line and a rear-stage input data enable signal fed back from an adjacent rear-stage timing controller through a second interface line which differs from the first interface line, at least one of the first to Nth timing controllers independently calculates an adjacent delay amount between itself and the rear-stage timing controller so as to generate the output data enable signal, and
wherein the plurality of pixels include a first micro LED chip for red emission, a second micro LED chip for green emission, and a third micro LED chip for blue emission.
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