US 12,148,358 B2
Scan circuit and display apparatus
Yao Huang, Beijing (CN); Meng Li, Beijing (CN); Tianyi Cheng, Beijing (CN); Doyoung Kim, Beijing (CN); and Long Ma, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/760,495
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Nov. 1, 2021, PCT No. PCT/CN2021/127843
§ 371(c)(1), (2) Date Aug. 10, 2022,
PCT Pub. No. WO2023/070647, PCT Pub. Date May 4, 2023.
Prior Publication US 2024/0185766 A1, Jun. 6, 2024
Int. Cl. G09G 3/32 (2016.01)
CPC G09G 3/32 (2013.01) [G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0223 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A scan circuit, comprising a plurality of stages;
wherein a respective stage of the scan circuit comprises a second processing subcircuit, which comprises a first capacitor, a sixth transistor, and a seventh transistor;
a first terminal of the first capacitor is coupled to a sixth node, and a second terminal of the first capacitor is coupled to a third node;
a gate electrode of the sixth transistor is coupled to the sixth node;
a first electrode of the sixth transistor is coupled to a third input terminal;
a second electrode of the sixth transistor is coupled to the third node;
a gate electrode of the seventh transistor is coupled to the third input terminal;
a first electrode of the seventh transistor is coupled to the third node;
a second electrode of the seventh transistor is coupled to a fourth node;
the respective stage of the scan circuit further comprises a sixth connecting line connecting a first electrode of the seventh transistor, a second electrode of the sixth transistor, and a second capacitor electrode of the first capacitor together; and
the sixth connecting line crosses over both a first capacitor electrode and the second capacitor electrode of the first capacitor;
wherein the first capacitor electrode of the first capacitor and the gate electrode of the sixth transistor are parts of a unitary structure; and
the first capacitor electrode of the first capacitor has a L shape, a first part of the first capacitor electrode extending substantially along a first direction, a second part of the first capacitor electrode extending substantially along a second direction;
wherein the respective stage of the scan circuit further comprises an input subcircuit comprising a first transistor, and an input signal line configured to provide an input signal to the first transistor, a portion of the input signal line extending substantially along the second direction;
a gate electrode of the first transistor is coupled to a second input terminal;
a first electrode of the first transistor is coupled to a first input terminal;
a second electrode of the first transistor is coupled to a fifth node; and
a ratio of a width along the first direction of the first part to a shortest distance between the first part and the portion extending substantially along the second direction is no more than 2.0:1.