	US 12,148,338 B2
	Display module including gate control chip and electronic terminal including the same
Yunhai Bai, Guangdong (CN); Guoqing Gao, Guangdong (CN); Xinying Luo, Guangdong (CN); Jinao Chen, Guangdong (CN); Jianzhong Xiao, Guangdong (CN); and Mingyao Chen, Guangdong (CN)
Assigned to SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Guangdong (CN)
Appl. No. 17/755,869
Filed by SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Guangdong (CN)
PCT Filed Apr. 18, 2022, PCT No. PCT/CN2022/087358 § 371(c)(1), (2) Date May 10, 2022, PCT Pub. No. WO2023/184608, PCT Pub. Date Oct. 5, 2023.
Claims priority of application No. 202210349713.3 (CN), filed on Apr. 2, 2022.
Prior Publication US 2024/0153422 A1, May 9, 2024
Int. Cl. G09G 3/20 (2006.01)

CPC G09G 3/20 (2013.01) [G09G 2300/0408 (2013.01); G09G 2330/021 (2013.01); G09G 2330/08 (2013.01)]

13 Claims

1. A display module, comprising:

a panel including a display area and a non-display area located on at least one side of the display area, wherein a gate driving circuit is disposed in the non-display area; and

a gate control chip including a first output pin and a second output pin, wherein both the first output pin and the second output pin are electrically connected to the gate driving circuit;

wherein, the gate control chip is configured to, when a first signal outputted from the first output pin is abnormal, control the second output pin to output a second signal, and control the first output pin not to output the first signal;

wherein, the panel includes:

an array substrate layer including the gate driving circuit;

a first circuit layer, located on the array substrate layer, including a first line, wherein the first line is electrically connected between the first output pin and the gate driving circuit;

a second circuit layer, located on the array substrate layer, including a second line, wherein the second line is electrically connected between the second output pin and the gate driving circuit, and the first circuit is disposed at a different layer from and insulated from the second circuit;

wherein, the gate control chip further includes:

a first input pin; and

an identification module, wherein the first input pin is electrically connected between the first output pin and the identification module, and the identification module is configured to identify when the first signal is abnormal, control the second output pin to output the second signal, and control the first output pin not to output the first signal;

wherein the identification module includes:

an identification unit, wherein an input end of the identification unit is electrically connected to the first input pin to receive the first signal;

a first output unit, wherein a control end of the first output unit is electrically connected to an output end of the identification unit, for outputting a first enable signal from a first output end of the first output unit to control the second output pin to output the second signal when the first signal is abnormal; and

a second output unit, wherein a control end of the second output unit is electrically connected to the output end of the identification unit, for outputting a second non-enable signal from a second output end of the second output unit to control the first output pin not to output the first signal when the first signal is abnormal;

wherein the first output unit is further configured to output a first non-enable signal from the first output unit to control the second output pin not to output the second signal when the first signal is not abnormal; and the second output unit is further configured to output a second enable signal from the second output unit to control the first output pin to output the first signal when the first signal is not abnormal;

wherein the gate control chip includes a plurality of the identification module, and the gate control chip further includes:

an OR circuit, wherein an input end of the OR circuit is electrically connected to a plurality of the first output end, for outputting a third enable signal from an output end of the OR circuit when the first signal is abnormal to control the second output pin to output the second signal; and

an AND circuit, wherein an input end of the AND circuit is electrically connected to a plurality of the second output end, for outputting a fourth enable signal from an output end of the AND circuit when the first signal is not abnormal to control the first output pin to output the first signal.