| CPC G07C 5/0808 (2013.01) [G07C 5/0816 (2013.01); H04L 12/40 (2013.01); H04W 12/122 (2021.01); H04L 2012/40215 (2013.01)] | 17 Claims |

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1. A system comprising:
memory;
a database including information indicating one or more latency values associated with a change of a state associated with one or more nodes on a communication bus, wherein the database further includes information indicative one or more messages configured to change the state of the one or more nodes and a list of packet sequences that cause state changes in the ECUs, wherein the latency values indicate latency of various state transition;
a secure processor in communication with the memory and programmed to:
monitor the one or more messages from a first node of the one or more modes on the communication bus, wherein the one or more messages include a request to a state change of the one or more nodes;
in response to the one or more messages including the request to the state change, initiate a timer to initiate monitoring of the communication bus for a second sequence of messages in a pre-defined time period;
determine whether the second sequence of messages are transmitted during a blind period; and
in response to the second sequence of messages not aligned with the database indicating packet information associated with one or more latency values associated with the change of the state and an unexpected packet sequence during the blind period, output a signal indicating an alert, and output the alert without analyzing contents of the second sequence of messages.
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