US 12,147,914 B2
Compression for deep learning in case of sparse values mapped to non-zero value
Ajit Singh, Bangalore (IN); Bharat Daga, Bangalore (IN); and Michael Behar, Israel (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 14, 2023, as Appl. No. 18/466,981.
Application 18/466,981 is a continuation of application No. 17/390,528, filed on Jul. 30, 2021, granted, now 11,763,183.
Application 17/390,528 is a continuation of application No. 15/853,457, filed on Dec. 22, 2017, granted, now 11,080,611.
Prior Publication US 2024/0078453 A1, Mar. 7, 2024
Int. Cl. G06F 13/10 (2006.01); G06F 13/28 (2006.01); G06F 17/16 (2006.01); G06N 3/04 (2023.01); G06N 3/08 (2023.01); G06N 5/046 (2023.01); G06N 20/00 (2019.01); G06T 9/00 (2006.01); G06T 15/20 (2011.01)
CPC G06N 5/046 (2013.01) [G06F 13/10 (2013.01); G06F 13/28 (2013.01); G06F 17/16 (2013.01); G06N 3/04 (2013.01); G06N 3/08 (2013.01); G06N 20/00 (2019.01); G06T 9/002 (2013.01); G06T 15/205 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A graphics processor comprising:
compute circuitry to generate neural network data for a neural network and write the neural network data to a memory; and
a direct memory access (DMA) controller including a hardware codec having an encode circuit and a decode circuit, the DMA controller to:
decode encoded kernel data for the neural network in association with a read of the encoded kernel data from the memory via the hardware codec within the DMA controller, wherein to decode the encoded kernel data includes to pre-fetch metadata associated with the encoded kernel data from a metadata storage location associated with the encoded kernel data, the encoded kernel data including losslessly encoded convolution filter data;
encode feature map data for a layer of the neural network, the feature map data generated via the compute circuitry, the feature map data encoded via the hardware codec of the DMA controller during a write to the memory;
decode encoded feature map data in association with a read of the encoded feature map data from the memory via the hardware codec within the DMA controller; and
process the feature map data as input feature map data for a next layer of the neural network.