US 12,147,892 B2
Electronic apparatus and controlling method thereof
Sejung Kwon, Suwon-si (KR); Baeseong Park, Suwon-si (KR); and Dongsoo Lee, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 8, 2020, as Appl. No. 16/843,365.
Claims priority of application No. 10-2019-0057261 (KR), filed on May 16, 2019.
Prior Publication US 2020/0364558 A1, Nov. 19, 2020
Int. Cl. G06N 3/08 (2023.01); G06N 3/04 (2023.01)
CPC G06N 3/08 (2013.01) [G06N 3/04 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An electronic apparatus comprising:
an off-chip memory; and
a processor coupled to the off-chip memory, the processor comprising a calculator, an on-chip primary cache memory and an on-chip secondary cache memory, the processor configured to:
obtain a first matrix and a second matrix by applying a singular value decomposition (SVD) to a first square matrix among a plurality of square matrices based on parameter values of a deep learning model,
obtain a first approximated matrix and a second approximated matrix for the first square matrix by applying a low rank approximation to the first matrix and the second matrix,
obtain second approximated matrices for each of a plurality of remaining square matrices other than the first square matrix among the plurality of square matrices, based on the first approximated matrix for the first square matrix, and
store, as a compressed deep learning model, the first approximated matrix for the first square matrix and the second approximated matrices for each of the plurality of square matrices in the off-chip memory,
wherein the calculator is configured to load from the off-chip memory into the on-chip primary cache memory the first approximated matrix, load from the off-chip memory into the on-chip secondary cache memory at least one second approximated matrix from among the second approximated matrices loaded from the off-chip memory into the on-chip secondary cache memory, and obtain an output value utilizing the compressed learning model based on the loaded first approximated matrix and the loaded at least one second approximated matrix,
wherein the calculator further is configured to load the at least one second approximated matrix from the off-chip memory into the on-chip secondary cache memory during execution of a first algorithm based on an input value and the loaded first approximated matrix, and
wherein the calculator is further configured to perform a second algorithm based on a result of the first algorithm and the loaded at least one second approximated matrix.