US 12,147,870 B2
Phase lock loop circuit based adjustment of a measurement time window in an optical measurement system
Ryan Field, Culver City, CA (US); Jacob Dahle, Arlington, MA (US); Rong Jin, Acton, MA (US); Bruno Do Valle, Brighton, MA (US); and Sebastian Sorgenfrei, Playa Vista, CA (US)
Assigned to HI LLC, Culver City, CA (US)
Filed by HI LLC, Los Angeles, CA (US)
Filed on Mar. 27, 2023, as Appl. No. 18/126,786.
Application 18/126,786 is a continuation of application No. 17/202,572, filed on Mar. 16, 2021, granted, now 11,645,483.
Claims priority of provisional application 62/992,497, filed on Mar. 20, 2020.
Claims priority of provisional application 63/027,018, filed on May 19, 2020.
Prior Publication US 2023/0229878 A1, Jul. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06K 7/10 (2006.01); G02B 27/01 (2006.01)
CPC G06K 7/10732 (2013.01) [G02B 27/0172 (2013.01); G06K 7/10851 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A system comprising:
a time-to-digital converter (TDC) configured to monitor for an occurrence of a photodetector output pulse during a measurement time window that is within and shorter in duration than a light pulse time period, the photodetector output pulse generated by a photodetector when the photodetector detects a photon from a light pulse having a light pulse time period;
a phase lock loop (PLL) circuit for the TDC and having a PLL feedback period defined by a reference clock, the PLL circuit configured to:
output a plurality of fine phase signals each having a different phase; and
output one or more signals representative of a plurality of feedback divider states during the PLL feedback period; and
a precision timing circuit connected to the PLL circuit and configured to:
adjust, based on at least one of one or more of the fine phase signals or the one or more signals representative of the feedback divider states, a temporal position of the measurement time window within the light pulse time period, and
set, based on a combination of one of the fine phase signals and one of the feedback divider states, a temporal position of a timing pulse within the PLL feedback period.