| CPC G06F 9/5083 (2013.01) [G06F 9/505 (2013.01); G06F 13/4239 (2013.01)] | 25 Claims |

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1. An apparatus comprising:
first computation circuitry of a first type;
interface circuitry to access a first work queue corresponding to the first computation circuitry and a second work queue corresponding to second computation circuitry of a second type;
load balancing instructions to obtain tasks from a workload by encoding first and second index ranges of a data parallel operation;
determination instructions to make a determination to move a task from the second work queue and add the task to the first work queue, the first computation circuitry and the second computation circuitry corresponding to a work-group, the determination to move the task after a determination that the first computation circuitry is a leader in the work-group and based on load balancing and at least one of processing speed or reduced power consumption; and
the first computation circuitry to cause the move of the task from the second work queue via an atomic operation, the atomic operation to perform a read operation and a write operation to update a pointer of the second work queue in a same bus cycle during the move of the task, the atomic operation to prevent multiple entities from moving the task.
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