US 12,147,813 B2
Method for handling exception or interrupt in heterogeneous instruction set architecture and apparatus
Yifei Jiang, Hangzhou (CN); Siqi Zhao, Shenzhen (CN); and Bo Wan, Hangzhou (CN)
Assigned to Huawei Technologies Co., Ltd., Shenzhen (CN)
Filed by HUAWEI TECHNOLOGIES CO., LTD., Guangdong (CN)
Filed on Dec. 12, 2022, as Appl. No. 18/064,543.
Application 18/064,543 is a continuation of application No. PCT/CN2021/096075, filed on May 26, 2021.
Claims priority of application No. 202010539884.3 (CN), filed on Jun. 12, 2020.
Prior Publication US 2023/0124004 A1, Apr. 20, 2023
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/455 (2018.01); G06F 9/48 (2006.01)
CPC G06F 9/3865 (2013.01) [G06F 9/3861 (2013.01); G06F 9/45558 (2013.01); G06F 9/4818 (2013.01); G06F 2009/45591 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method for handling an exception, wherein the method comprises:
when a secondary architecture virtual machine triggers an exception, obtaining, by a virtual machine monitor of a physical host that comprises a primary processor core supporting a primary instruction set architecture and a secondary processor core supporting a secondary instruction set architecture, status information of the exception from a shared memory that is shared by the secondary processor core and the primary processor core, wherein the status information of the exception comprises first code of the exception, and the first code of the exception indicates a type of the exception in the secondary instruction set architecture, wherein the physical host further comprises a secondary architecture register, and wherein the status information of the exception is copied by the secondary processor core from the secondary architecture register to the shared memory, and the secondary architecture register is a register that complies with a specification of the secondary instruction set architecture and that is configured to store the status information of the exception;
obtaining, by the virtual machine monitor, second code of the exception from an exception mapping relationship, wherein the second code of the exception indicates a type of the exception in the primary instruction set architecture, and the exception mapping relationship comprises a correspondence between first code and second code of each type of exception among a plurality of types of exceptions; and
identifying, by the virtual machine monitor, the type of the exception based on the second code of the exception, and handling the exception.