| CPC G06F 9/30036 (2013.01) [G06F 7/485 (2013.01); G06F 7/4876 (2013.01); G06F 7/762 (2013.01); G06F 9/3001 (2013.01); G06F 9/30032 (2013.01); G06F 9/30043 (2013.01); G06F 9/30109 (2013.01); G06F 9/30112 (2013.01); G06F 9/30134 (2013.01); G06F 9/30145 (2013.01); G06F 9/30149 (2013.01); G06F 9/3016 (2013.01); G06F 9/30185 (2013.01); G06F 9/30196 (2013.01); G06F 9/3818 (2013.01); G06F 9/3836 (2013.01); G06F 17/16 (2013.01); G06F 2212/454 (2013.01)] | 21 Claims |

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1. A processor comprising:
decode circuitry to decode an instance of a single instruction having fields for an opcode, an identifier for a first source multidimensional matrix operand, an identifier of a second source multidimensional matrix operand, and an identifier for a source/destination multidimensional matrix operand; and
execution circuitry to execute the decoded instance of the single instruction to multiply the identified first source multidimensional matrix operand by the identified second source multidimensional matrix operand, add a result of the multiplication to the identified source/destination multidimensional matrix operand, and store a result of the addition in the identified source/destination multidimensional matrix operand.
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