US 12,147,784 B2
Compute in memory
Po-Hao Lee, Hsinchu (TW); Chia-Fu Lee, Hsinchu (TW); Yi-Chun Shih, Taipei (TW); Yu-Der Chih, Hsin-Chu (TW); Hidehiro Fujiwara, Hsin-Chu (TW); Haruki Mori, Hsinchu (TW); and Wei-Chang Zhao, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 28, 2021, as Appl. No. 17/387,598.
Claims priority of provisional application 63/143,467, filed on Jan. 29, 2021.
Prior Publication US 2022/0244916 A1, Aug. 4, 2022
Int. Cl. G06F 7/544 (2006.01); G11C 11/412 (2006.01)
CPC G06F 7/5443 (2013.01) [G11C 11/412 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A compute-in-memory (CIM) device, comprising:
a memory array including a plurality of memory cells arranged in rows and columns, the plurality of memory cells including a first memory cell in a first row and a first column of the memory array and a second memory cell in the first row and a second column of the memory array, the first and second memory cells configured to store respective first and second weight signals;
an input driver configured to provide a plurality of input signals;
a first logic circuit coupled to the first memory cell and configured to provide a first output signal based on a first input signal from the input driver and the first weight signal;
a second logic circuit coupled to the second memory cell and configured to provide a second output signal based on a second input signal from the input driver and the second weight signal; and
an adder circuit configured to add weight sign signals associated with the first and second weight signals.