US 12,147,783 B2
Pipelined hardware to accelerate modular arithmetic operations
Rajat Rao, Bangalore (IN)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Apr. 28, 2021, as Appl. No. 17/242,351.
Prior Publication US 2022/0350570 A1, Nov. 3, 2022
Int. Cl. G06F 17/16 (2006.01); G06F 7/544 (2006.01); G06F 7/72 (2006.01); H04L 9/30 (2006.01)
CPC G06F 7/5443 (2013.01) [G06F 7/725 (2013.01); H04L 9/3066 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method comprising:
determining a bit width of operands in data to be processed by a modular hardware block; and
in response to there being a mismatch between the bit width of the operands and a fixed bit width of the modular hardware block, modifying the operands to be accommodated by the fixed bit width of the modular hardware block and causing the modular hardware block to process the operands, wherein:
the modular hardware block comprises a first multiplication accumulator connected in series to a second multiplication accumulator such that the second multiplication accumulator is connected in series to a third multiplication accumulator, the first and second multiplication accumulators being connected to a correction block;
performing, by the first multiplication accumulator, a first operation in order to output first high order bits to the second multiplication accumulator and output first low order bits to the correction block;
performing, by the second multiplication accumulator, a second operation in order to output second high order bits to the third multiplication accumulator; and
performing by the third multiplication accumulator, a third operation in order to output third low order bits to the correction block.