US 12,147,782 B2
Peripheral tooldual/quad-fracturable digital signal processing block for programmable gate architectures
Ho Man Ho, Hong Kong (CN)
Assigned to EFINIX, INC., Santa Clara, CA (US)
Filed by EFINIX, INC., Santa Clara, CA (US)
Filed on Jul. 29, 2021, as Appl. No. 17/389,128.
Claims priority of provisional application 63/168,017, filed on Mar. 30, 2021.
Claims priority of provisional application 63/168,009, filed on Mar. 30, 2021.
Prior Publication US 2022/0317970 A1, Oct. 6, 2022
Int. Cl. G06F 7/487 (2006.01); G06F 7/485 (2006.01); G06F 7/544 (2006.01)
CPC G06F 7/4876 (2013.01) [G06F 7/485 (2013.01); G06F 7/5443 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A digital signal processor (DSP), comprising:
a fracturable multiplier;
a fracturable adder;
a fracturable variable shifter; and
at least one sign-extension block that is configured to provide sign extension across modes of the DSP comprising normal mode, dual-fracturing mode and quad-fracturing mode, wherein:
the fracturable multiplier, in the normal mode, comprises a 19×18 multiplier;
the fracturable multiplier, in the dual-fracturing mode, comprises an 11×10 multiplier for a most significant bit (MSB) lane and an 8×8 multiplier for a least significant bit (LSB) lane; or
the fracturable multiplier, in the quad-fracturing mode, comprises a 7×6 multiplier for the MSB lane and a 4×4 multiplier for each of three other lanes.