US 12,147,751 B2
Integrated circuit and method of designing the same
Seungman Lim, Siheung-si (KR); Hakchul Jung, Seoul (KR); Sanghoon Baek, Seoul (KR); Jaewoo Seo, Seoul (KR); Jisu Yu, Seoul (KR); and Hyeongyu You, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 28, 2021, as Appl. No. 17/360,355.
Claims priority of application No. 10-2020-0106431 (KR), filed on Aug. 24, 2020.
Prior Publication US 2022/0058331 A1, Feb. 24, 2022
Int. Cl. G06F 30/3953 (2020.01); G06F 30/327 (2020.01); G06F 119/06 (2020.01); H01L 23/528 (2006.01)
CPC G06F 30/3953 (2020.01) [H01L 23/5286 (2013.01); G06F 30/327 (2020.01); G06F 2119/06 (2020.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a plurality of logic cells in a first row extending in a first direction, the plurality of logic cells including different types of active areas extending in the first direction;
a filler cell in a second row extending in the first direction, the second row being adjacent to the first row in a second direction with a height thereof being different from a height of the first row, the second direction being orthogonal to the first direction;
a first routing wiring line in the second row, the first routing wiring line configured to connect a first logic cell and a second logic cell among the plurality of logic cells, the first logic cell and the second logic cell being spaced apart from each other by a first distance; and
a second routing wiring line in the second row, the second routing wiring line configured to connect a third logic cell and a fourth logic cell among the plurality of logic cells.