US 12,147,713 B2
High-bandwidth DDR DIMM, memory system, and operation method thereof
Liang Zhang, Zhuhai (CN); Jiayun Zhang, Zhuhai (CN); Jiechen Shou, Zhuhai (CN); Chuanhao Xu, Zhuhai (CN); and Ming Huang, Zhuhai (CN)
Assigned to INNOSILICON MICROELECTRONICS (ZHUHAI) CO., LTD., Zhuhai (CN)
Filed by INNOSILICON MICROELECTRONICS (ZHUHAI) CO., LTD., Zhuhai (CN)
Filed on Dec. 14, 2022, as Appl. No. 18/081,640.
Application 18/081,640 is a continuation of application No. PCT/CN2022/121590, filed on Sep. 27, 2022.
Claims priority of application No. 202210952285.3 (CN), filed on Aug. 9, 2022.
Prior Publication US 2024/0053898 A1, Feb. 15, 2024
Int. Cl. G06F 3/06 (2006.01); G06F 1/12 (2006.01); G11C 7/10 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01)
CPC G06F 3/0673 (2013.01) [G06F 1/12 (2013.01); G11C 7/1042 (2013.01); G11C 7/109 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A high-bandwidth double data rate (DDR) dual-in-line memory module (DIMM), comprising: a first sub-channel, a second sub-channel, a register and divided clock driver, and a combined data buffer, wherein the first sub-channel comprises a first pseudo channel and a second pseudo channel, the second sub-channel comprises a third pseudo channel and a fourth pseudo channel, each pseudo channel comprising a plurality of dynamic random-access memory (DRAM) chips; the register and divided clock driver is configured to determine a command mode in response to a command sent by a host and send the command to the first pseudo channel, the second pseudo channel, the third pseudo channel, and/or the fourth pseudo channel according to the command mode; and the combined data buffer is configured to interleave data of the first pseudo channel and the second pseudo channel.