US 12,147,712 B2
Memory performance using memory access command queues in memory devices
Sundararajan N. Sankaranarayanan, Fremont, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 8, 2023, as Appl. No. 18/533,727.
Application 18/533,727 is a continuation of application No. 17/411,572, filed on Aug. 25, 2021, granted, now 11,868,655.
Prior Publication US 2024/0103770 A1, Mar. 28, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0622 (2013.01); G06F 3/0679 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system comprising:
a controller; and
a memory device comprising a first plane and a second plane, each plane associated with a respective queue maintained by a respective local media controller of the memory device, wherein the controller is configured to perform operations comprising:
storing, in a first queue associated with the first plane, a first plurality of memory access commands;
storing, in a second queue associated with the second plane, a second plurality of memory access commands; and
processing the first plurality of memory access commands from the first queue and the second plurality of memory access commands from the second queue.