US 12,147,702 B2
Host training indication for memory artificial intelligence
Nicolas Soberanes, Boise, ID (US); Ezra E. Hartz, Boise, ID (US); Jonathan S. Parry, Boise, ID (US); Bruce J. Ford, Meridian, ID (US); Joseph A. De La Cerda, Boise, ID (US); and Benjamin Rivera, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 20, 2022, as Appl. No. 17/579,995.
Prior Publication US 2023/0229352 A1, Jul. 20, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 12/0811 (2016.01); G06F 18/214 (2023.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0625 (2013.01); G06F 3/0679 (2013.01); G06F 12/0811 (2013.01); G06F 18/214 (2023.01)] 22 Claims
OG exemplary drawing
 
1. A method, comprising:
determining, at an artificial intelligence (AI) component of a host, whether to train an AI accelerator of a memory sub-system;
responsive to determining to train the AI accelerator, determining, at the AI component, a training category corresponding to a memory access request, wherein the training category describes resources of the memory sub-system utilized to process corresponding commands; and
providing an indication to the memory sub-system that causes training of the AI accelerator to be performed based on the training category,
wherein a training is performed using the AI accelerator, utilizing a queue depth, opcode, chunk size logical block address (LBA) range, and time stamp of the memory access request and responsive to providing the indication, and
wherein an output of the AI accelerator is used to process the memory access request in a single-level cell (SLC) mode or a multi-level cell (MLC) mode.