| CPC G06F 3/0635 (2013.01) [G06F 3/0625 (2013.01); G06F 3/0679 (2013.01)] | 22 Claims |
|
1. A method, comprising;
receiving, by an address circuitry of a memory device, signaling indicative of first sensed temperatures detected by a first plurality of temperature sensors directly connected to a first memory die within a stack of memory dies;
wherein the first plurality of temperature sensors are each in a different physical location on the first memory die;
receiving, by the address circuitry of the memory device, signaling indicative of second sensed temperatures detected by a second plurality of temperature sensors directly connected to a second memory die within the stack of memory dies;
wherein the second plurality of temperature sensors are each in a different physical location on the second memory die;
receiving, by the address circuitry of the memory device, signaling indicative of third sensed temperatures detected by a third plurality of temperature sensors directly connected to a third memory die within the stack of memory dies,
wherein the third plurality of temperature sensors are each in a different physical location on the third memory die;
wherein respective temperature sensors of the first plurality of temperature sensors and respective temperature sensors of the third plurality of temperature sensors are physically vertically aligned in respective three-dimensional cross-sections of the stack of memory dies, and
wherein the second plurality of temperature sensors are in staggered arrangement within the stack of memory dies versus the first plurality of temperature sensors and the third plurality of temperature sensors, such that the second plurality of temperature sensors are outside of the respective three-dimensional cross-sections of the stack of memory dies;
identifying, based at least in part on the first, second, and third sensed temperatures and respective positions of the first, second, and third plurality of temperature sensors within the stack of memory dies, a portion of the memory device experiencing an excessive operating temperature; and
remapping logical addresses of a first memory bank of the first memory die within a threshold number of physical addresses of the identified portion of the memory device to physical addresses of a second memory bank of the first memory die that is further away from the identified portion of memory device than the first memory bank.
|