	US 12,147,675 B2
	Memory module
Haruhiko Terada, Kanagawa (JP); Yotaro Mori, Kanagawa (JP); Riichi Nishino, Kanagawa (JP); and Yoshiyuki Shibahara, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 17/997,862
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Apr. 16, 2021, PCT No. PCT/JP2021/015770 § 371(c)(1), (2) Date Nov. 3, 2022, PCT Pub. No. WO2021/230003, PCT Pub. Date Nov. 18, 2021.
Claims priority of application No. 2020-083231 (JP), filed on May 11, 2020.
Prior Publication US 2023/0229313 A1, Jul. 20, 2023
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 12/10 (2016.01)

CPC G06F 3/0611 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 12/10 (2013.01); G06F 2212/1024 (2013.01)]

16 Claims

1. A memory module, comprising:

a non-volatile memory including:

a first address bus terminal of a first system of two systems;

a second address bus terminal of a second system of the two systems; and

a plurality of writable non-volatile memory cells;

address lookup information which is mapping information indicating a correspondence relationship between a physical address and a logical address,

wherein the physical address specifies a data storage region based on a first number of writable non-volatile memory cells of the plurality of writable non-volatile memory cells; and

a controller configured to:

convert, upon reception of a read command including the logical address, the logical address included in the read command into the physical address using the address lookup information, wherein the conversion of the logical address into the physical address comprises:

convert a first logical address, which is a first portion of the logical address included in the read command, into a first physical address,

wherein the first physical address is a first portion of the physical address obtained by the conversion of the physical address; and

convert a second logical address, which is a second portion of the logical address included in the read command, into a second physical address, wherein

the second portion of the logical address is different from the first portion of the logical address,

the second physical address is a second portion of the physical address, and

the second portion of the physical address is different from the first portion of the physical address;

input the first physical address, to the non-volatile memory via the first address bus terminal,

wherein the second logical address is converted into the second physical address within a first period in which the first physical address is inputted to the non-volatile memory via the first address bus terminal; and

input the second physical address to the non-volatile memory via the second address bus terminal; and

read data, corresponding to the physical address obtained by the conversion, from the non-volatile memory based on the first physical address and the second physical address.