US 12,147,671 B2
Performance match method of memory, memory storage device and memory control circuit unit
Chih-Ling Wang, Anhui (CN); Dong Dong Yao, Anhui (CN); Yun Peng Zhang, Anhui (CN); Kuai Cao, Anhui (CN); En Yang Wang, Anhui (CN); and Wen Qing Lv, Anhui (CN)
Assigned to Hefei Core Storage Electronic Limited, Anhui (CN)
Filed by Hefei Core Storage Electronic Limited, Anhui (CN)
Filed on Mar. 27, 2023, as Appl. No. 18/190,147.
Claims priority of application No. 202310184472.6 (CN), filed on Feb. 24, 2023.
Prior Publication US 2024/0289017 A1, Aug. 29, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/061 (2013.01) [G06F 3/0634 (2013.01); G06F 3/0679 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A performance match method of memory, configured in a memory storage device, the performance match method of the memory comprising:
receiving a performance match command from a host system, wherein the performance match command is configured to provide performance requirement information of the host system to the memory storage device, and the performance requirement information reflects at least one of storage space required by the host system to be forcibly released in an idle state of the memory storage device, and a current value of the memory storage device required by the host system in a low power consumption mode;
in response to the performance match command, adjusting an operation setting of a memory storage device to match a performance of the memory storage device with a performance requirement of the host system; and
interacting with the host system based on an adjusted operation setting.