US 12,147,670 B2
Method and apparatus for performing data access management of memory device in predetermined communications architecture with aid of unbalanced table regions
Jie-Hao Lee, Hsinchu County (TW); Chien-Cheng Lin, Yilan County (TW); and Chang-Chieh Huang, Hsinchu County (TW)
Assigned to Silicon Motion, Inc., Hsinchu County (TW)
Filed by Silicon Motion, Inc., Hsinchu County (TW)
Filed on Jan. 9, 2023, as Appl. No. 18/094,396.
Prior Publication US 2024/0231624 A1, Jul. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 12/1009 (2016.01)
CPC G06F 3/061 (2013.01) [G06F 3/064 (2013.01); G06F 3/0679 (2013.01); G06F 12/1009 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method for performing data access management of a memory device in a predetermined communications architecture with aid of unbalanced table regions, the method being applied to a memory controller of the memory device, the memory device comprising the memory controller and a non-volatile (NV) memory, the NV memory comprising at least one NV memory element, the at least one NV memory element comprising a plurality of blocks, the method comprising:
utilizing the memory controller to receive a first command from a host device through a transmission interface circuit of the memory controller, wherein the first command carries first information related to first data to be written, the first information comprises at least one first logical address for indicating at least one first logical address region, and the first command indicates that writing the first data into the at least one first logical address region is requested;
performing a first checking operation on the first information to generate a first determination result, wherein the first determination result indicates whether the first data belongs to hot data or cold data, and the hot data and the cold data represent frequently accessed data and infrequently accessed data, respectively;
determining a selected active block among multiple active blocks according to the first determination result and according to at least one predetermined rule, where the multiple active blocks comprise a hybrid active block and a hot active block for receiving hybrid data and a first portion of the hot data, respectively, and the hybrid data comprises the cold data and another portion of the hot data; and
receiving the first data with the selected active block, and updating a temporary physical-to-logical (P2L) address mapping table corresponding to the selected active block, for generating or updating a P2L address mapping table in the NV memory for performing subsequent processing, wherein the temporary P2L address mapping table is one of multiple temporary P2L address mapping tables respectively corresponding to the multiple active blocks, and the multiple temporary P2L address mapping tables are arranged to occupy table regions of different sizes in a Random Access Memory (RAM) within the memory controller, respectively.