CPC G06F 3/061 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 2212/7203 (2013.01)] | 18 Claims |
1. A memory device comprising:
a first memory group including a first non-volatile memory cell configured to store multi-bit data; and
a control device configured to:
perform plural program operations to store the multi-bit data in the first non-volatile memory cell;
perform, in response to a read command before most significant bit data among the multi-bit data is programmed into the first non-volatile memory cell, a read operation for obtaining bit data, which has been programmed in the first non-volatile memory cell among the multi-bit data, according to a program state of the first non-volatile memory cell while the plural program operations are performed; and
output the bit data obtained in response to the read command,
wherein the control device comprises a data buffer, which comprises volatile memory cells and is configured to temporarily store write data including the multi-bit data to be stored in the first non-volatile memory cell, and
wherein the control device is further configured to remove a part of the write data, corresponding to the bit data, from the data buffer, after the bit data has been programmed in the first non-volatile memory cell and before all of the multi-bit data is programmed in the first non-volatile memory cell.
|