US 12,147,532 B2
Performance monitoring unit of a processor deterring tampering of counter configuration and enabling verifiable data sampling
Rahuldeva Ghosh, Portland, OR (US); and Zheng Zhang, Portland, OR (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 1, 2021, as Appl. No. 17/539,698.
Prior Publication US 2022/0092174 A1, Mar. 24, 2022
Int. Cl. G06F 21/71 (2013.01); G06F 9/455 (2018.01); G06F 11/34 (2006.01); G06F 21/44 (2013.01); G06F 21/53 (2013.01); G06F 21/54 (2013.01); G06F 21/55 (2013.01); G06F 21/56 (2013.01); G06F 21/57 (2013.01); G06F 21/60 (2013.01); G06F 21/64 (2013.01); H04L 9/08 (2006.01); H04L 9/32 (2006.01)
CPC G06F 21/54 (2013.01) [G06F 11/3466 (2013.01); G06F 21/44 (2013.01); G06F 21/566 (2013.01); G06F 21/57 (2013.01); H04L 9/3242 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
processor circuitry coupled to a memory, the processor circuitry to facilitate a secure group manager to:
receive a request to create a secure counter group from a software (SW) process being executed by a processor, the request including identification of one or more performance monitoring counters;
determine availability of the one or more performance monitoring counters, creating the secure counter group, assign the one or more performance monitoring counters to the secure counter group, and save a public key of the SW process, when the one or more performance monitoring counters are available;
receive and save a private key for the secure counter group;
receive a request to configure the secure counter group from the SW process;
verify the configuration using the public key of the SW process; and
start sampling of the one or more performance monitoring counters when the configuration is verified.