US 12,147,367 B2
Folded memory modules
Amir Amirkhany, Sunnyvale, CA (US); Suresh Rajan, San Jose, CA (US); Ravindranath Kollipara, Palo Alto, CA (US); Ian Shaeffer, Los Gatos, CA (US); and David A. Secker, San Jose, CA (US)
Assigned to RAMBUS INC., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Jul. 20, 2023, as Appl. No. 18/355,660.
Application 18/355,660 is a continuation of application No. 17/809,688, filed on Jun. 29, 2022, granted, now 11,755,521.
Application 17/809,688 is a continuation of application No. 16/950,861, filed on Nov. 17, 2020, granted, now 11,409,682, issued on Aug. 9, 2022.
Application 16/950,861 is a continuation of application No. 16/525,315, filed on Jul. 29, 2019, granted, now 10,866,916, issued on Dec. 15, 2020.
Application 16/525,315 is a continuation of application No. 15/289,785, filed on Oct. 10, 2016, granted, now 10,380,053, issued on Aug. 13, 2019.
Application 15/289,785 is a continuation of application No. 14/182,986, filed on Feb. 18, 2014, granted, now 9,489,323, issued on Nov. 8, 2016.
Claims priority of provisional application 61/767,097, filed on Feb. 20, 2013.
Prior Publication US 2024/0020258 A1, Jan. 18, 2024
Int. Cl. G06F 13/40 (2006.01); G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/16 (2006.01)
CPC G06F 13/4022 (2013.01) [G06F 12/00 (2013.01); G06F 13/00 (2013.01); G06F 13/1673 (2013.01); G06F 13/1694 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory module comprising:
a plurality of memory ranks including at least a first memory rank having at least a first memory device and a second memory rank having at least a second memory device;
a plurality of data pins including at least a first group of data pins and a second group of data pins;
switching logic to switch data between the first group of data pins and one of the first memory rank and the second memory rank dependent on a select signal, and to switch data between the second group of data pins and one of the first memory rank and the second memory rank dependent on the select signal;
a first plurality of configurable switches coupled between the first group of data pins and the switching logic controllable to enable or disable a coupling between the first group of data pins and the switching logic;
a second plurality of configurable switches coupled between the second group of data pins and the switching logic controllable to enable or disable a coupling between the second group of data pins and the switching logic;
a select line to receive the select signal to control the switching logic; and
configuration control lines to control the first plurality of configurable switches and the second plurality of configurable switches.