US 12,147,362 B2
Deterministic operation of storage class memory
Frederick A. Ware, Los Altos Hills, CA (US); and Brent Haukness, Sunnyvale, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Aug. 29, 2023, as Appl. No. 18/239,681.
Application 18/239,681 is a continuation of application No. 17/715,404, filed on Apr. 7, 2022, granted, now 11,755,509.
Application 17/715,404 is a continuation of application No. 16/660,768, filed on Oct. 22, 2019, granted, now 11,314,669, issued on Apr. 26, 2022.
Application 16/660,768 is a continuation of application No. 15/376,507, filed on Dec. 12, 2016, granted, now 10,467,157, issued on Nov. 5, 2019.
Claims priority of provisional application 62/268,436, filed on Dec. 16, 2015.
Prior Publication US 2024/0054084 A1, Feb. 15, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/16 (2006.01)
CPC G06F 13/1689 (2013.01) 20 Claims
OG exemplary drawing
 
1. A memory controller comprising:
a transfer interface configured to issue address information associated with a write operation to a bank of a memory device, the transfer interface configured to generate a time value, the time value representing a minimum time interval after which a subsequent write operation can be issued to the bank;
write queue logic including an issue queue configured to temporarily store the address information and the time value; and
wherein the transfer interface is responsive to expiration of the minimum time interval to issue the subsequent write operation to the bank of the memory device.