US 12,147,351 B2
Heterogenous-latency memory optimization
Evan Lawrence Erickson, Chapel Hill, NC (US); Christopher Haywood, Cary, NC (US); and Mark D. Kellam, Siler City, NC (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Apr. 25, 2023, as Appl. No. 18/139,220.
Application 18/139,220 is a continuation of application No. 17/543,449, filed on Dec. 6, 2021, granted, now 11,663,138.
Claims priority of provisional application 63/123,439, filed on Dec. 9, 2020.
Prior Publication US 2023/0333989 A1, Oct. 19, 2023
Int. Cl. G06F 12/10 (2016.01); G06F 12/0804 (2016.01); G06F 12/0882 (2016.01); G06F 12/1009 (2016.01); G06F 12/123 (2016.01); G06F 13/16 (2006.01)
CPC G06F 12/1009 (2013.01) [G06F 12/0804 (2013.01); G06F 12/0882 (2013.01); G06F 12/123 (2013.01); G06F 13/1668 (2013.01); G06F 2212/7201 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of operation within a computing system, the method comprising:
iteratively relocating respective sets of memory pages from an operating memory to an access-counting memory such that each one of the sets of memory pages is relocated in a respective one of a sequence of memory migration intervals;
during each one of the memory migration intervals, generating, for constituent memory pages of the one of the sets of memory pages relocated to the access-counting memory, respective multi-bit count values that indicate respective numbers of accesses directed to the constituent memory pages during the one of the memory migration intervals; and
selectively relocating the constituent memory pages from the access-counting memory to the operating memory based on the multi-bit count values;
wherein generating respective multi-bit count values comprises incrementing each one of the multi-bit count values in response to each access to the corresponding one of the memory pages during the one of the memory migration intervals.