US 12,147,350 B2
Integrated circuit and method for cleaning valid bits in cache memory of the integrated circuit
Yung-Chi Lan, Taichung (TW)
Assigned to NUVOTON TECHNOLOGY CORPORATION, Hsinchu Science Park (TW)
Filed by Nuvoton Technology Corporation, Hsinchu Science Park (TW)
Filed on May 18, 2023, as Appl. No. 18/319,708.
Claims priority of application No. 111132592 (TW), filed on Aug. 30, 2022.
Prior Publication US 2024/0070085 A1, Feb. 29, 2024
Int. Cl. G06F 12/0895 (2016.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 12/0868 (2016.01); G06F 12/0891 (2016.01); G06F 13/16 (2006.01)
CPC G06F 12/0895 (2013.01) [G06F 3/0679 (2013.01); G06F 12/0238 (2013.01); G06F 12/0868 (2013.01); G06F 12/0891 (2013.01); G06F 13/1668 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a processor;
a cache memory, comprising a plurality of addresses, wherein each of the addresses comprises a valid bit, a tag, and a data column;
a cache memory controller, configured to control access to the cache memory;
a flash memory; and
a flash memory controller, configured to control access to the flash memory;
wherein when the integrated circuit is booted up or enters a working state from a sleep mode, the cache memory controller performs a valid-bit-cleaning process to sequentially clean the valid bit corresponding to each of the addresses in the cache memory;
wherein in response to the flash memory controller reading data corresponding to a specific address from the flash memory, the flash memory controller notifies the cache memory controller to suspend the valid-bit-cleaning process, and the cache memory controller then writes the data into the specific address of the cache memory, writes a mapping address corresponding to the specific address into the tag corresponding to the specific address of the cache memory, and sets the valid bit corresponding to the specific address as valid;
wherein in response to the valid bit corresponding to the specific address of the cache memory being set as valid, the cache memory controller reads the data from the specific address of the cache memory and transmits the data to the processor, and resumes the valid-bit-cleaning process.