US 12,147,349 B2
Processor and operation thereof to revoke cache memory states utilizing write-back buffer
Taeweon Suh, Namyangju-si (KR); Gunjae Koo, Namyangju-si (KR); Jongmin Lee, Seoul (KR); and Junyeon Lee, Suwon-si (KR)
Assigned to Korea University Research and Business Foundation, Seoul (KR)
Filed by Korea University Research and Business Foundation, Seoul (KR)
Filed on Dec. 15, 2022, as Appl. No. 18/081,921.
Claims priority of application No. 10-2021-0179950 (KR), filed on Dec. 15, 2021.
Prior Publication US 2023/0185724 A1, Jun. 15, 2023
Int. Cl. G06F 12/0875 (2016.01); G06F 12/0891 (2016.01); G06F 12/123 (2016.01)
CPC G06F 12/0875 (2013.01) [G06F 12/0891 (2013.01); G06F 12/123 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A processor for performing a speculative execution for an out-of-order execution, the processor comprising:
a core; and
an L1 cache memory,
wherein the core includes
a speculative track buffer (STB) storing speculative track information in order to track a speculative instruction when the speculative instruction is recorded in a reorder buffer (ROB), and
a load queue (LQ) transmitting a commit doorbell signal or a restore doorbell signal for a first speculative block to which a first speculative instruction belongs to the L1 cache memory based on first speculative track information of the first speculative instruction when a speculative success or a speculative failure of the first speculative instruction included in the speculative instruction is decided, and
the L1 cache memory includes a write buffer, and
the write buffer stores an evicted cache block evicted from a tag and data area of the L1 cache memory as a request generated by the speculative instruction is returned to the L1 cache memory, and performs a commit operation or a restore operation for the evicted cache block corresponding to the first speculative block when receiving a commit doorbell signal or a restore doorbell signal for the first speculative block.