US 12,147,340 B2
Address scheduling methods for non-volatile memory devices with three- dimensional memory cell arrays
Chi Weon Yoon, Seoul (KR); Dong Hyuk Chae, Seoul (KR); Sang-Wan Nam, Hwaseong-si (KR); and Jung-Yun Yun, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 4, 2023, as Appl. No. 18/312,109.
Application 18/312,109 is a continuation of application No. 17/137,942, filed on Dec. 30, 2020, granted, now 11,681,616.
Application 17/137,942 is a continuation of application No. 16/849,645, filed on Apr. 15, 2020, granted, now 10,909,032, issued on Feb. 2, 2021.
Application 16/849,645 is a continuation of application No. 15/790,583, filed on Oct. 23, 2017, granted, now 10,671,529, issued on Jun. 2, 2020.
Application 15/790,583 is a continuation in part of application No. 14/837,857, filed on Aug. 27, 2015, granted, now 9,798,659, issued on Oct. 24, 2017.
Application 14/837,857 is a continuation of application No. 13/213,806, filed on Aug. 19, 2011, abandoned.
Claims priority of application No. 10-2010-0080964 (KR), filed on Aug. 20, 2010.
Prior Publication US 2023/0273880 A1, Aug. 31, 2023
Int. Cl. G06F 12/06 (2006.01); G06F 3/06 (2006.01); G11C 5/02 (2006.01); G11C 8/10 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01)
CPC G06F 12/0646 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01); G11C 5/025 (2013.01); G11C 8/10 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G06F 2212/2022 (2013.01); G11C 2211/5648 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of programming a three dimensional NAND flash memory device including a first sub-block, a second sub-block, and a first plurality of cell strings coupled to a first bit line, the first plurality of cell strings comprising a first cell string and a second cell string,
the first sub-block including a first plurality of word lines configured with a first word line and a second word line, and first nonvolatile memory cells coupled to the first plurality of word lines,
the second sub-block including a second plurality of word lines configured with a third word line and a fourth word line, and second nonvolatile memory cells coupled to the second plurality of word lines,
each of the first plurality of cell strings including a plurality of nonvolatile memory cells connected serially, the plurality of nonvolatile memory cells being stacked on or above a substrate in a direction perpendicular to the substrate,
at least one memory cell included in the nonvolatile memory cells of the first sub-block and the second sub-block corresponding to a multi-bit memory cell which is configured to store N-bit data where “N” is a natural number greater than or equal to 2, the method comprising:
selecting the first cell string of the first plurality of cell strings which is coupled to the first bit line;
programming sequentially, address scheduling the first nonvolatile memory cells in order from the first word line to the second word line; and
programming sequentially, address scheduling the second nonvolatile memory cells in order from the third word line to the fourth word line;
wherein the order of the address scheduling for the first plurality of word lines of the first sub-block is different to the order of the address scheduling for the second plurality of word lines of the second sub-block, and
wherein the first sub-block and the second sub-block are separated by at least one dummy word line.