US 12,147,334 B2
Apparatus and method for searching for logical address ranges of host commands
Chun-Yu Chen, Taitung County (TW)
Assigned to SILICON MOTION, INC., Zhubei (TW)
Filed by Silicon Motion, Inc., Zhubei (TW)
Filed on Sep. 15, 2023, as Appl. No. 18/369,046.
Claims priority of application No. 202211479927.9 (CN), filed on Nov. 24, 2022.
Prior Publication US 2024/0176734 A1, May 30, 2024
Int. Cl. G06F 12/02 (2006.01); G06F 12/06 (2006.01); H03K 3/037 (2006.01)
CPC G06F 12/0246 (2013.01) [G06F 12/0653 (2013.01); H03K 3/037 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus for searching for logical address ranges of host commands, comprising:
a second start register, arranged operably to store a second start logical address;
a second end register, arranged operably to store a second end logical address;
a first comparator comprising a first input terminal, a second input terminal and a first output terminal, wherein the first input terminal is coupled to a first end register, the second input terminal is coupled to the second start register, and the first output terminal is arranged operably to output logic “0” to a NOR gate when a first end logical address stored in the first end register is not smaller than the second start logical address;
a second comparator comprising a third input terminal, a fourth input terminal and a second output terminal, wherein the third input terminal is coupled to the second end register, the fourth input terminal is coupled to a first start register, and the second output terminal is arranged operably to output logic “0” to the NOR gate when the second end logical address is not smaller than a first start logical address stored in the first start register;
the NOR gate comprising a fifth input terminal, a sixth input terminal and a third output terminal, wherein the fifth input terminal is coupled to the first output terminal, the sixth input terminal is coupled to the second output terminal, and the third output terminal is arranged operably to output logic “1” to a matching register and an output circuitry when both the fifth input terminal and the sixth input terminal receive logic “0”; and
the output circuitry, arranged operably to output a memory address of a random access memory (RAM) storing a second logical address range from the second start logical address to the second end logical address to a resulting address register when receiving logic “1” from the NOR gate.