US 12,147,302 B2
Systems and methods for error detection and control for embedded memory and compute elements
Vasanth Ranganathan, El Dorado Hills, CA (US); Joydeep Ray, Folsom, CA (US); Abhishek R. Appu, El Dorado Hills, CA (US); Nikos Kaburlasos, Folsom, CA (US); Lidong Xu, Beijing (CN); Subramaniam Maiyuran, Gold River, CA (US); Altug Koker, El Dorado Hills, CA (US); Naveen Matam, Rancho Cordova, CA (US); James Holland, Folsom, CA (US); Brent Insko, Portland, OR (US); Sanjeev Jahagirdar, Folsom, CA (US); Scott Janus, Loomis, CA (US); Durgaprasad Bilagi, Folsom, CA (US); and Xinmin Tian, Union City, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 11, 2020, as Appl. No. 17/095,530.
Claims priority of provisional application 62/935,773, filed on Nov. 15, 2019.
Prior Publication US 2021/0149763 A1, May 20, 2021
Int. Cl. G06F 11/10 (2006.01); G06F 12/0802 (2016.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 12/0802 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06F 2212/70 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A graphics multiprocessor, comprising:
memory of the graphics multiprocessor for storing data, wherein the memory is cache or local memory; and
error detection correction circuitry having error registers and integrated with the memory of the graphics multiprocessor, the error detection correction circuitry is configured to perform a tag read of the memory to determine whether error detection correction information of error detection and correction logic indicates an error condition or not, and to report the error condition to the error registers to log a source of a correctable error when a correctable error occurs or to report the error condition to the error registers to report an uncorrectable error when an uncorrectable error occurs, wherein the error detection correction circuitry is located on chip or on die with the graphics multiprocessor.