US 12,147,301 B2
Parallelized scrubbing transactions
David Matthew Thompson, Dallas, TX (US); and Abhijeet Ashok Chachad, Plano, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on May 30, 2023, as Appl. No. 18/325,181.
Application 18/325,181 is a continuation of application No. 16/882,377, filed on May 22, 2020, granted, now 11,675,660.
Claims priority of provisional application 62/852,465, filed on May 24, 2019.
Prior Publication US 2023/0297469 A1, Sep. 21, 2023
Int. Cl. G06F 11/10 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/448 (2018.01); G06F 9/46 (2006.01); G06F 9/48 (2006.01); G06F 9/52 (2006.01); G06F 12/0811 (2016.01); G06F 12/0815 (2016.01); G06F 12/0879 (2016.01); G06F 12/0888 (2016.01); G06F 12/0895 (2016.01); G06F 12/128 (2016.01); G06F 13/16 (2006.01); H03M 13/15 (2006.01)
CPC G06F 11/106 (2013.01) [G06F 9/30047 (2013.01); G06F 9/30101 (2013.01); G06F 9/3867 (2013.01); G06F 9/4498 (2018.02); G06F 9/467 (2013.01); G06F 9/4812 (2013.01); G06F 9/52 (2013.01); G06F 11/1064 (2013.01); G06F 11/1068 (2013.01); G06F 12/0811 (2013.01); G06F 12/0879 (2013.01); G06F 12/0895 (2013.01); G06F 13/1668 (2013.01); H03M 13/1575 (2013.01); G06F 12/0815 (2013.01); G06F 12/0888 (2013.01); G06F 12/128 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/608 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a processor core; and
a cache subsystem coupled to the processor core that includes:
a first memory block;
a first pipeline circuit coupled to the first memory block;
a second memory block;
a second pipeline circuit coupled to the second memory block;
a register configured to store a scrubbing enable field, a scrubbing burst delay field, and a scrubbing cycle delay field; and
a controller coupled to the first pipeline circuit, the second pipeline circuit, and the register, wherein the controller is configured to, based on a value stored in the register:
cause the first pipeline circuit to perform a first scrubbing transaction on the first memory block;
cause the second pipeline circuit to perform a second scrubbing transaction on the second memory block; and
cause the second pipeline circuit to perform a transaction that is not a scrubbing transaction on the second memory block during the performing of the first scrubbing transaction.