US 12,147,264 B2
Clock distribution circuit and semiconductor apparatus including the same preliminary class
Ji Hyo Kang, Icheon-si (KR); Kyung Hoon Kim, Icheon-si (KR); Jae Hyeok Yang, Icheon-si (KR); Sang Yeon Byeon, Icheon-si (KR); Gang Sik Lee, Icheon-si (KR); and Joo Hyung Chae, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Mar. 14, 2023, as Appl. No. 18/183,799.
Application 18/183,799 is a continuation in part of application No. 17/226,952, filed on Apr. 9, 2021, granted, now 11,625,062.
Claims priority of application No. 10-2020-0155737 (KR), filed on Nov. 19, 2020.
Prior Publication US 2023/0213961 A1, Jul. 6, 2023
Int. Cl. G06F 1/10 (2006.01); G11C 7/22 (2006.01); H03K 19/00 (2006.01)
CPC G06F 1/10 (2013.01) [G11C 7/222 (2013.01); H03K 19/0016 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A clock distribution circuit comprising:
a global distribution circuit configured to receive external clock signals and configured to generate internal clock signals and primary reference clock signal set according to the external clock signals;
a first local distribution circuit configured to receive the internal clock signals and the primary reference clock signal set and configured to generate a secondary reference clock signal set according to the internal clock signals and the primary reference clock signal set; and
a second local distribution circuit configured to receive the internal clock signals and the secondary reference clock signal set and configured to generate a thirdly reference clock signal set according to the internal clock signals and the secondary reference clock signal set.