US 12,147,263 B2
Low power system on chip
Kyuseung Han, Daejeon (KR); Tae Wook Kang, Daejeon (KR); Sung Eun Kim, Daejeon (KR); Hyuk Kim, Daejeon (KR); Hyung-Il Park, Daejeon (KR); Kwang Il Oh, Daejeon (KR); and Jae-Jin Lee, Daejeon (KR)
Assigned to ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, Daejeon (KR)
Filed by Electronics and Telecommunications Research Institute, Daejeon (KR)
Filed on Jun. 23, 2022, as Appl. No. 17/847,636.
Claims priority of application No. 10-2021-0082973 (KR), filed on Jun. 25, 2021.
Prior Publication US 2022/0413544 A1, Dec. 29, 2022
Int. Cl. G06F 1/00 (2006.01); G06F 1/10 (2006.01); G06F 15/78 (2006.01)
CPC G06F 1/10 (2013.01) [G06F 15/7817 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A network on chip, comprising:
a first clock gate circuit (CG)-network interface that supports communication of a first intellectual property (IP) block;
a second CG-network interface that supports communication of a second IP block; and
a clock gating controller,
wherein the clock gating controller receives a clock gating request from the first IP block, outputs a communication control signal to the second CG-network interface in response to the received clock gating request, and performs a clock gating operation for a clock signal in response to the received clock gating request to selectively deliver the clock signal to the second IP block, and
wherein the communication control signal is either:
a signal requesting the second CG-network interface not to allow communication with the second IP block, when the received clock gating request indicates blocking a clock of the second IP block; or
a signal requesting the second CG-network interface to allow communication with the second IP block, when the received clock gating request indicates unblocking the clock of the second IP block.