US 12,147,209 B2
Microcontroller unit and corresponding method of operation
Rosario Martorana, Catania (IT); Mose' Alessandro Pernice, Patyerno' (IT); and Roberto Colombo, Munich (DE)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT); and STMicroelectronics Application GmbH, Aschheim-Dornach (DE)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT); and STMicroelectronics Application GmbH, Aschheim-Dornach (DE)
Filed on Mar. 25, 2022, as Appl. No. 17/704,675.
Claims priority of application No. 102021000007703 (IT), filed on Mar. 29, 2021.
Prior Publication US 2022/0308545 A1, Sep. 29, 2022
Int. Cl. G05B 19/042 (2006.01)
CPC G05B 19/0428 (2013.01) [G05B 2219/24015 (2013.01); G05B 2219/25257 (2013.01)] 21 Claims
OG exemplary drawing
 
15. A method of checking integrity of configuration data of a microcontroller unit that includes a set of configuration memory locations configured to store configuration data and a hardware monitoring module coupled to the configuration memory locations, the method comprising:
i) reading a command from an instruction memory, said command including a start address and a number of consecutive memory accesses for a target memory location in said set of configuration memory locations;
ii) reading data from the start address and number of consecutive memory accesses for said target memory location;
iii) computing a checksum value as a function of said data that was read;
iv) comparing said computed checksum value to a respective expected checksum value stored in a checksum storage unit; and
v) triggering an alarm signal in response to a mismatch detected between said computed checksum value and said respective expected checksum value.