US 12,147,201 B2
Segmented digital-to-time converter
Abhishek Bhat, Allentown, PA (US); Ajay Bharadwaj, Breinigsville, PA (US); and Romesh Kumar Nandwana, Chapel Hill, NC (US)
Assigned to CISCO TECHNOLOGY, INC., San Jose, CA (US)
Filed by Cisco Technology, Inc., San Jose, CA (US)
Filed on Nov. 17, 2022, as Appl. No. 17/989,045.
Prior Publication US 2024/0168442 A1, May 23, 2024
Int. Cl. H03D 3/24 (2006.01); G04F 10/00 (2006.01); H03L 7/099 (2006.01)
CPC G04F 10/005 (2013.01) [H03L 7/0992 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A digital-to-time converter comprising:
a plurality of delay stages arranged in series, wherein a first delay stage of the plurality of delay stages is configured to receive an input clock signal and a last delay stage of the plurality of delay stages is configured to provide an output clock signal; and
a plurality of local synchronization logic circuits each configured to control an associated delay stage of the plurality of delay stages, wherein each local synchronization logic circuit provides a digital-to-time converter code and a reset signal to the associated delay stage synchronized to a local input clock and a local output clock of the associated delay stage.