US 12,146,927 B2
Magnetoresistive random access memory and method for fabricating the same
Hui-Lin Wang, Taipei (TW); Chen-Yi Weng, New Taipei (TW); Che-Wei Chang, Taichung (TW); Si-Han Tsai, Taichung (TW); Ching-Hua Hsu, Kaohsiung (TW); Jing-Yin Jhang, Tainan (TW); and Yu-Ping Wang, Hsinchu (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Oct. 4, 2023, as Appl. No. 18/376,451.
Application 18/376,451 is a continuation of application No. 16/927,918, filed on Jul. 13, 2020, granted, now 11,821,964.
Claims priority of application No. 202010546950.X (CN), filed on Jun. 16, 2020.
Prior Publication US 2024/0027549 A1, Jan. 25, 2024
Int. Cl. G01R 33/09 (2006.01); G11C 11/02 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01)
CPC G01R 33/093 (2013.01) [G01R 33/098 (2013.01); G11C 11/02 (2013.01); H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a magnetic tunneling junction (MTJ) on a substrate, wherein the MTJ comprises:
a pinned layer on the substrate;
a barrier layer on the pinned layer;
a reference layer between the barrier layer and the pinned layer, wherein the reference layer comprises a first width and a second width, the first width is a different width than the second width, the first width is in a direction parallel with the second width, and a sidewall of the second width of the reference layer is aligned with a sidewall of the pinned layer; and
a free layer on the barrier layer.