US 12,146,912 B1
Clock gating circuits and methods for dual-edge-triggered applications
Arnab Khawas, Bangalore (IN); Gokul Sabada, Bangalore (IN); Madhavan Sainath Rao Pissay, Hyderabad (IN); and Badarish Subbannavar, Bangalore (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Apr. 27, 2023, as Appl. No. 18/308,486.
Int. Cl. G01R 31/3185 (2006.01); G01R 31/317 (2006.01)
CPC G01R 31/318552 (2013.01) [G01R 31/31724 (2013.01); G01R 31/31727 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
an oscillator configured to output a clock signal;
a clock gating system coupled to the oscillator; and
a data storage circuit coupled to the clock gating system;
wherein the clock gating system comprises:
a first digital logic circuit that includes a first input coupled to the oscillator to receive the clock signal, a second input, and an output;
an active-low latch circuit that includes a first input coupled to the output of the first digital logic circuit, a second input configured to receive an enable signal, and an output;
a second digital logic circuit that includes a first input coupled to the oscillator to receive the clock signal, a second input coupled to the output of the active-low latch circuit, and an output; and
an active-high latch circuit that includes a first input coupled to the output of the second digital logic circuit, a second input configured to receive the enable signal, and an output configured to provide a gated clock signal; and
wherein the data storage circuit includes a clock input coupled to the output of the active-high latch circuit to receive the gated clock signal.