US 12,146,911 B1
TVF transition coverage with self-test and production-test time reduction
Venkata Narayanan Srinivasan, Greater Noida (IN); Manish Sharma, Gurgaon (IN); Jeena Mary George, Kattappana (IN); and Umesh Chandra Srivastava, Greater Noida (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on May 30, 2023, as Appl. No. 18/203,345.
Int. Cl. G01R 31/3185 (2006.01)
CPC G01R 31/318541 (2013.01) [G01R 31/318536 (2013.01); G01R 31/318552 (2013.01); G01R 31/318555 (2013.01); G01R 31/318572 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a control circuit comprising a first flip-flop, a second flip-flop, a first OR gate, and a second OR gate, an output of each flip-flop coupled to its respective input, a reset terminal of each flip-flop configured to receive a scan mode signal, a scan in terminal of the first flip-flop configured to receive a scan in signal, a first input of the first OR gate coupled to the output of the first flip-flop, a second input of the first OR gate coupled to a scan enable signal, a first input of the second OR gate coupled to the output of the second flip-flop, a second input of the second OR gate coupled to the scan enable signal, and the output of the first flip-flop coupled to scan in terminal of the second flip-flop; and
a triple-voting flop comprising N number of scan flip-flops, N being an odd number greater than or equal to 3, the N scan flip-flops comprising a first scan flip-flop, a second scan flip-flop, and a third scan flip-flop, the first scan flip-flop having an output coupled to a scan input of the second scan flip-flop and a scan enable input coupled to an output terminal of the first OR gate of the control circuit, the third scan flip-flop having a scan input coupled to an output of the second scan flip-flop and a scan enable input coupled to an output terminal of the second OR gate of the control circuit, the control circuit configured to control the scan enable input of the first scan flip-flop and the scan enable input of the third scan flip-flop based on the scan enable signal and the scan mode signal.