US 12,146,906 B2
TFT panel and test method
Chongyu Zhu, Shanghai (CN); Libo Jin, Shanghai (CN); and Huan Yue, Shanghai (CN)
Assigned to IRAY TECHNOLOGY COMPANY LIMITED, Shanghai (CN)
Appl. No. 17/430,716
Filed by IRAY TECHNOLOGY COMPANY LIMITED, Shanghai (CN)
PCT Filed Oct. 18, 2019, PCT No. PCT/CN2019/111829
§ 371(c)(1), (2) Date Aug. 13, 2021,
PCT Pub. No. WO2020/164249, PCT Pub. Date Aug. 20, 2020.
Claims priority of application No. 201910112908.4 (CN), filed on Feb. 13, 2019.
Prior Publication US 2022/0146565 A1, May 12, 2022
Int. Cl. G01R 31/26 (2020.01); H01L 27/12 (2006.01)
CPC G01R 31/2621 (2013.01) [H01L 27/124 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A thin-film transistor (TFT) panel, comprising:
m×n bonding pads, wherein m and n are both natural numbers greater than or equal to 1, and the m×n bonding pads are arranged correspondingly to and electrically connected to TFT units in a TFT active area; and
a TFT test area, comprising m drive pads, n test pads, and m×n TFT devices, wherein the m×n TFT devices are divided into n groups, each group comprises m TFT devices, the m TFT devices in each group correspond to and are electrically connected to the m drive pads and m bonding pads respectively, and the m TFT devices in each group are electrically connected to a same test pad of the n test pads;
wherein m and n comprise natural numbers causing m+n to be less than m×n;
wherein the range of the ratio of a pitch between the adjacent drive pads to a pitch between the adjacent bonding pads comprises a range of from 5 to 20, and the range of the ratio of a pitch between the adjacent test pads to a pitch between the adjacent bonding pads comprises a range of from 5 to 20.