US 12,145,518 B2
Managing power in an integrated circuit for high-speed activation
Shubhendu Sekhar Mukherjee, Southborough, MA (US); and William Chu, Fremont, CA (US)
Assigned to Marvell Asia Pte, Ltd., Singapore (SG)
Filed by Marvell Asia Pte, Ltd., Singapore (SG)
Filed on Aug. 23, 2023, as Appl. No. 18/454,151.
Application 18/454,151 is a continuation of application No. 16/930,976, filed on Jul. 16, 2020, granted, now 11,766,975.
Claims priority of provisional application 62/875,439, filed on Jul. 17, 2019.
Prior Publication US 2023/0391281 A1, Dec. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/324 (2019.01); B60R 16/03 (2006.01); G06F 1/3293 (2019.01); G06F 9/4401 (2018.01)
CPC B60R 16/03 (2013.01) [G06F 1/324 (2013.01); G06F 1/3293 (2013.01); G06F 9/4406 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system-on-a-chip (SoC) comprising:
a first set of two or more processor cores configured to execute code, during operation of the SoC following activation, using an amount of power lower than a nominal power limit;
a second set of one or more processor cores, the second set of one or more processor cores constituting a subset of processor cores among the first set of two or more processor cores, configured to execute code during an activation time interval using an amount of power greater than the nominal power limit to boot functionality of the SoC;
an interconnect configured to communicate with two or more electronically controllable devices; and
circuitry configured to cause:
after the activation time interval, the second set of one or more processor cores to execute code during continued operation using an amount of power lower than the nominal power limit,
after booting functionality of the SoC, at least one processor core that is in the first set or the second set to execute code to activate control of a first electronically controllable device of the two or more electronically controllable devices, and
after activating control of the first electronically controllable device, at least one processor core that is in the first set or the second set to execute code to activate control of a second electronically controllable device of the two or more electronically controllable devices different from the first electronically controllable device.