US 12,145,360 B2
Integrated circuits including memory cells
Scott A. Linn, Corvallis, OR (US); James Michael Gardner, Corvallis, OR (US); and Michael W. Cumbie, Corvallis, OR (US)
Assigned to Hewlett-Packard Development Company, L.P., Spring, TX (US)
Filed by Hewlett-Packard Development Company, L.P., Spring, TX (US)
Filed on Dec. 21, 2023, as Appl. No. 18/393,224.
Application 18/393,224 is a continuation of application No. 17/471,844, filed on Sep. 10, 2021, granted, now 11,938,722.
Application 17/471,844 is a continuation of application No. 16/956,316, granted, now 11,141,973, issued on Oct. 12, 2021, previously published as PCT/US2019/016732, filed on Feb. 6, 2019.
Prior Publication US 2024/0116293 A1, Apr. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. B41J 2/045 (2006.01)
CPC B41J 2/04536 (2013.01) [B41J 2/04586 (2013.01); B41J 2/04541 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit to access a memory associated with a fluid ejection device, the integrated circuit comprising:
a plurality of memory cells;
an address decoder to select memory cells based on a data signal;
activation logic to activate selected memory cells based on the data signal and a fire signal; and
configuration logic to enable or disable access to the plurality of memory cells.