US 12,477,963 B2
CMOS-compatible resistive random-access memory devices with a via device structure
Mingche Wu, San Jose, CA (US); Minxian Zhang, Amherst, MA (US); and Ning Ge, Danville, CA (US)
Assigned to TetraMem Inc., San Jose, CA (US)
Filed by TetraMem Inc., Fremont, CA (US)
Filed on Sep. 29, 2022, as Appl. No. 17/936,830.
Prior Publication US 2024/0114813 A1, Apr. 4, 2024
Int. Cl. H10B 63/00 (2023.01); H10N 70/00 (2023.01)
CPC H10N 70/8833 (2023.02) [H10B 63/80 (2023.02); H10N 70/023 (2023.02); H10N 70/063 (2023.02); H10N 70/066 (2023.02); H10N 70/068 (2023.02); H10N 70/841 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first resistive random-access memory (RRAM) device, comprising:
a first bottom electrode fabricated on a first interconnect layer;
a first top electrode;
a first filament-forming layer fabricated between the first bottom electrode and the first top electrode, wherein the first filament-forming layer comprises at least one switching metal oxide, and wherein a first filament-forming region of the first filament-forming layer and at least a portion of the first top electrode are fabricated in a first via in a first etch stop layer;
a second etch stop layer fabricated on the first top electrode;
a dielectric layer fabricated on the second etch stop layer; and
a first metal via of a second interconnect layer fabricated in the second etch stop layer and the dielectric layer, wherein the first top electrode is connected to a bitline through the first metal via of the second interconnect layer;
wherein a critical device size of the first RRAM device is defined by a dimension of the first filament-forming region and an opening size of the first metal via.
 
14. A method, comprising:
fabricating one or more bottom electrodes on a substrate comprising a first interconnect layer;
fabricating a first etch stop layer on the substrate and the one or more bottom electrodes;
fabricating one or more vias in the first etch stop layer to expose a portion of each of the bottom electrodes;
fabricating a switching oxide layer on the first etch stop layer, wherein at least a portion of the switching oxide layer is fabricated on the exposed portion of the bottom electrodes;
fabricating a top electrode layer on the switching oxide layer;
fabricating a second etch stop layer on the switching oxide layer; and
fabricating one or more top electrodes by selectively removing one or more portions of the second etch stop layer and the top electrode layer.