| CPC H10F 39/804 (2025.01) [H10F 39/809 (2025.01); H10F 39/811 (2025.01); H01L 24/16 (2013.01); H01L 2224/16225 (2013.01)] | 20 Claims |

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1. A chip package, comprising:
a first semiconductor chip having a first surface and a second surface opposite the first surface;
a second semiconductor chip stacked on the second surface and having a third surface facing the second surface and a fourth surface opposite the third surface;
a first encapsulating layer surrounding the first semiconductor chip;
a second encapsulating layer surrounding the second semiconductor chip;
a first through-via penetrating through the first encapsulating layer; and
a second through-via, penetrating through the second encapsulating layer and electrically connected between the second semiconductor chip and the first through-via,
wherein the first surface is an active surface of the first semiconductor chip and the fourth surface is an active surface of the second semiconductor chip.
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