US 12,477,831 B2
Semiconductor device having interleaved clock gate blocks and decoupling capacitor blocks and method of operating same
Liu Han, Hsinchu (TW); Xin Yong Wang, Hsinchu (TW); Qingchao Meng, Hsinchu (TW); Huaixin Xian, Hsinchu (TW); and Jing Ding, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); TSMC CHINA COMPANY, LIMITED, Shanghai (CN); and TSMC NANJING COMPANY, LIMITED, Nanjing (CN)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); TSMC NANJING COMPANY, LIMITED, Jiangsu (CN); and TSMC CHINA COMPANY, LIMITED, Shanghai (CN)
Filed on Aug. 10, 2023, as Appl. No. 18/447,857.
Application 18/447,857 is a division of application No. 17/406,643, filed on Aug. 19, 2021.
Claims priority of application No. 202110849010.2 (CN), filed on Jul. 21, 2021.
Prior Publication US 2023/0402446 A1, Dec. 14, 2023
Int. Cl. H10D 89/10 (2025.01); H03K 19/00 (2006.01); H10D 84/80 (2025.01)
CPC H10D 89/10 (2025.01) [H03K 19/0016 (2013.01); H10D 84/811 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device having a cell region, the cell region comprising:
a first set of first pairs of substantially uniformly sized first blocks, each of the first blocks including a clock gate; and
a second set of second pairs of substantially uniformly sized second blocks, each of the second blocks including a decoupling capacitor; and
wherein:
at least one of:
the first set has two or more first pairs; or
the second set has two or more second pairs; and
the first pairs of the first set are interleaved with the second pairs of the second set into (A) columns and one or more rows or (B) rows and one or more columns such that:
at least some of the first pairs of the first set and at least some of the second pairs of the second set are arranged in a first one of the rows with respect to a first direction; and
each odd-numbered first pair in the first row is a corresponding one of the first pairs and each even-numbered pair in the first row is a corresponding one of the second pairs.