US 12,477,815 B2
Semiconductor device
Tomoyuki Obata, Matsumoto (JP); Soichi Yoshida, Matsumoto (JP); Tetsutaro Imagawa, Matsumoto (JP); and Seiji Momota, Matsumoto (JP)
Assigned to FUJI ELECTRIC CO., LTD., Kanagawa (JP)
Filed by FUJI ELECTRIC CO., LTD., Kanagawa (JP)
Filed on Sep. 27, 2023, as Appl. No. 18/476,284.
Application 17/577,048 is a division of application No. 16/693,367, filed on Nov. 24, 2019, granted, now 11,239,234, issued on Feb. 1, 2022.
Application 18/476,284 is a continuation of application No. 17/577,048, filed on Jan. 17, 2022, granted, now 11,810,914.
Application 16/693,367 is a continuation of application No. PCT/JP2018/037481, filed on Oct. 5, 2018.
Claims priority of application No. 2017-239713 (JP), filed on Dec. 14, 2017.
Prior Publication US 2024/0021607 A1, Jan. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 84/80 (2025.01); H10D 12/00 (2025.01); H10D 62/13 (2025.01); H10D 84/60 (2025.01)
CPC H10D 84/811 (2025.01) [H10D 12/211 (2025.01); H10D 62/133 (2025.01); H10D 84/617 (2025.01)] 29 Claims
OG exemplary drawing
 
1. A semiconductor device having a first trench portion repetitive region and a second trench portion repetitive region, the semiconductor device comprising:
a gate metal layer provided above an upper surface of a semiconductor substrate;
an emitter electrode provided above the upper surface of the semiconductor substrate;
a first conductivity-type emitter region provided on an upper surface side of the semiconductor substrate at least in the first trench portion repetitive region;
one or more gate trench sections provided on the upper surface side of the semiconductor substrate at least in the first trench portion repetitive region, electrically connected to the gate metal layer and being in contact with the emitter region;
one or more emitter trench sections provided on the upper surface side of the semiconductor substrate in the first trench portion repetitive region and the second trench portion repetitive region and electrically connected to the emitter electrode; and
one or more dummy trench sections provided on the upper surface side of the semiconductor substrate, electrically connected to the gate metal layer and being not in contact with the emitter region.