US 12,477,813 B2
Metal gates for multi-gate semiconductor devices and method thereof
Chih-Wei Lee, New Taipei (TW); Jo-Chun Hung, Hsinchu (TW); Wen-Hung Huang, Hsin-Chu (TW); Jian-Hao Chen, Hsinchu (TW); and Kuo-Feng Yu, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jun. 5, 2022, as Appl. No. 17/832,649.
Prior Publication US 2023/0395435 A1, Dec. 7, 2023
Int. Cl. H01L 21/02 (2006.01); H01L 21/28 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/038 (2025.01) [H01L 21/02603 (2013.01); H01L 21/28088 (2013.01); H10D 30/014 (2025.01); H10D 30/031 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6739 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 84/0167 (2025.01); H10D 84/0177 (2025.01); H10D 84/85 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
providing a structure having a substrate, a first stack of nanostructures spaced vertically one from another over a surface of the substrate, and a second stack of nanostructures spaced vertically one from another over the surface of the substrate;
forming a dielectric layer wrapping around each of the nanostructures in the first and second stacks;
depositing an n-type work function layer on the dielectric layer, wherein the n-type work function layer wraps around each of the nanostructures in the first stack;
depositing a p-type work function layer on the n-type work function layer and over the first and second stacks, wherein the p-type work function layer wraps around each of the nanostructures in the second stack, wherein the depositing of the p-type work function layer increases an oxygen concentration in the n-type work function layer; and
forming an electrode layer on the p-type work function layer and over the first and second stacks.